Integrated circuits are an integral part of any electronic device. A variety of integrated circuits are often used together to enable the operation of the electronic device. While integrated circuits are typically designed for a particular application, one type of integrated circuit which enables flexibility is a programmable logic device. A programmable logic device (PLD) is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream, typically from off-chip memory, into configuration memory cells of the FPGA. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a programmable logic device to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, such as a read-only memory (ROM) (e.g. a programmable ROM (PROM), an erasable PROM (EPROM), or an electrically erasable PROM (EEPROM)) either external or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of a configuration logic block. The configuration bits not only configure the logic blocks, but also the dimensions of the RAMs to have a certain depth (i.e. number of rows) and width (i.e. length of a word in a row). At the end of this start-up phase, the PLD is now specialized to the user's design, and the PLD enters into a “user” mode as part of its normal operation. While PLDs provide flexibility in the implementation of a circuit, it is important to optimize the resources of the PLD, such as the available logic and interconnect resources. Accordingly, it is useful to reduce the logic necessary to implement a given circuit whenever possible.
In many electronic designs, it is necessary to implement a large addressable memory space. Another type of integrated circuit that is found in electronic devices is a memory, such as a random access memory (RAM). Depending upon the requirements of the circuit, RAM may be provided by one or more separate integrated circuits. Such an address space is often larger than the size of a standard RAM available to the designer. Therefore, the address space requires more than one RAM to implement the necessary memory, and data from the various RAMs may need to be multiplexed to get the desired output. A common way to structure the RAM array is to align the RAMs into rows of fixed depth. As shown for example in FIG. 1, each RAM of a plurality of RAMs 102 has a fixed arrangement comprising 512 rows of 36 bit words (i.e. 512×36). Each RAM is coupled to a multiplexer 104 for selecting an output of one of the RAMs. A control circuit 106 coupled to receive control signals and input data controls a read/write logic circuit 108 to enable writing data to a RAM or reading data from a RAM. While conventional configurable logic devices comprise blocks of RAM, often called BRAMs, having configurable dimensions, such blocks for a given application are chosen to have a word size for that application. The size of the RAM is selected so that the RAMs are all of the same size and have a width for storing words of a predetermined width, such as 36 bit words in this example. However, such arrangements require more complex logic arrangements to implement the RAMs, leading to inefficient use of logic resources. That is, the selection logic circuitry for selecting a row of a given RAM increases with the number of RAMs having the addressable row.
Accordingly, there is a need for an improved circuit for and method of configuring a memory array.